module crc32(
	input wire	clk,
	input wire	reset,
	input wire	enable,
	input wire	[7:0] data,
	output wire	[31:0] crc
);

reg [31:0] crc_reg;
reg [7:0] data_reg;
reg last_enable;

wire [31:0] crc_table_out;
wire [31:0] new_crc;
wire [7:0] crc_table_index;

assign crc_table_index = data_reg ^ crc_reg[7:0];

crc32_rom crctable_unit(.addr(crc_table_index), .data(crc_table_out));

always @(posedge clk)
begin
	if (reset) begin
		crc_reg <= 32'hffffffff;
		last_enable <= 0;
	end else begin
		if (last_enable)
			crc_reg <= crc_table_out ^ { 8'h00, crc_reg[31:8] };

		data_reg <= data;
		last_enable <= enable;
	end
end

assign crc = crc_reg ^ 32'hffffffff;

endmodule