`timescale 1ns/1ns

module test_crc32;
	reg	clk, reset, enable;
	reg [7:0] data;
	wire [31:0] crc;
	integer success;

	crc32 crc32_unit(
		.clk(clk),
		.reset(reset),
		.enable(enable),
		.data(data),
		.crc(crc)
	);

	initial begin
		$dumpfile("test_crc32.vcd");
		$dumpvars(0, test_crc32);

		repeat (100)
			@(posedge clk);

		$finish;
	end

	always
	begin
		reset = 1;
		enable = 0;
		data = 8'h00;
		#10;

		reset = 0;
		enable = 1;
		data = 8'h61;
		#2;

		reset = 0;
		enable = 1;
		data = 8'h62;
		#2;

		reset = 0;
		enable = 1;
		data = 8'h63;
		#2;

		reset = 0;
		enable = 1;
		data = 8'h64;
		#2;

		reset = 0;
		enable = 1;
		data = 8'h0a;

		#2;
		reset = 0;
		enable = 0;

		#2;
		if (crc != 32'h588aa4ac)
			$display("FAILED");
		else
			$display("SUCCESS -- CRC calculated correctly");

		reset = 0;
		enable = 0;

		#2;
		if (crc != 32'h588aa4ac)
			$display("FAILED -- CRC not held");
		else
			$display("SUCCESS -- CRC held correctly");

		reset = 1;
		enable = 0;

		#2;
		if (crc != 32'h00000000)
			$display("FAILED");
		else
			$display("SUCCESS -- CRC reset correctly");
		#2;
	end

	always
	begin
		clk = 1'b1;
		#1;
		clk = 1'b0;
		#1;
	end
endmodule // test