library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity mainvled is Port ( clk : in std_logic; led : out std_logic_vector(7 downto 0)); end mainvled; architecture Behavioral of mainvled is signal cnt : std_logic_vector(31 downto 0); signal val : std_logic_vector(7 downto 0); signal dir : std_logic; begin process begin wait until rising_edge(clk); cnt <= cnt + 1; if val = 0 then val <= "00000001"; end if; if X"000000" = (cnt and X"000fffff") then --0 is left if dir = '0' then if val = "10000000" then dir <= '1'; else val <= val(6 downto 0) & "0"; end if; else --1 is right if val = "00000001" then dir <= '0'; else val <= "0" & val(7 downto 1); end if; end if; led <= val; end if; end process; end Behavioral;